Better FPGA Verification with VHDL (Part 1): OSVVM Leading Edge Verification for the VHDL Community

Similar Tracks
Visualising software architecture with the C4 model - Simon Brown, Agile on the Beach 2019
Agile on the Beach
Trump Thanks Qatar for Their Generous Jet Bribe & Accidentally Does a Socialism | The Daily Show
The Daily Show
Trump Slammed for Qatar Bribe, Blinks on China Trade, Insults Pirro and Oz: A Closer Look
Late Night with Seth Meyers